ABSTRACT

Vending Machine is a soft drink dispensor machine that dispenses drink based on the amount deposited in the machine. It accepts all the coins ie: One(1 Rupee), Two(2 Rupees), Five(5 Rupees). Till it recieves 30 Rupees it will not dispense anything. After it has recieved 40 cents it will dispense a softdrink. Any amount above that will be given back as a change.

It's a melay or moore FSM based Design, vending machine is designed and implemented on EDA tools using verilog HDL. 



ABSTRACT

A shop security alarm in the Drug Shop has a sensor that catches items that try to go out the door without being purchased. A sensor will get activated if such an item attempts to escape, and a alarm will start ringing. so after restoring the item back alarm has to be stoped.

Using FSM, design is implemented. Synthesis of Verilog code is done using ISE Xilinx Suit.



ABSTRACT

Routing is the process of moving a packet of data from source to destination and enables messages to pass from one computer to another and eventually reach the target machine. A router is a networking device that forwards data packets between computer networks. It is connected to two or more data lines from different networks (as opposed to a network switch, which connects data lines from one single network). It mainly emphasizes upon the study of router device, it‟s top level architecture, and how various sub-modules of router i.e. Register, FIFO, FSM and Synchronizer are synthesized, and simulated and finally connected to its top module.



ABSTRACT

This article describes an 8-bit RISC processor design using Verilog Hardware Description Language (HDL) on FPGA board. The proposed processor is designed using Harvard architecture, having separate instruction and data memory. The salient feature of proposed processor is pipelining, used for improving performance, such that on every clock cycle one instruction will be executed. Another important feature is that instruction set contains only 34 instructions, which is very simple, easy to learn and compact. The proposed processor has 8-bit ALU, Two 8-bit I/O ports, serial-in/serial-out ports, Eight 8-bit general-purpose registers, 4-bit flag register and priority based three vectored interrupts. Another advantage of the proposed processor is that it can execute programs with up to 262,144 instructions long, such that any practical programs can be fitted into it. The proposed processor is physically verified on Xilinx Spartan 3E Starter Board FPGA with 0.0517μs instruction cycle.



ABSTRACT

 Because of rich applications, smart operating systems on cell phones are now being migrated to home appliances like televisions. However, applications that are originally designed to be operated by touch screen are not suitable for televisions with these systems. This paper presents a method to manipulate applications with infrared remote control instead of touch screen on televisions without rewriting the code of these applications or adding extra expense on hardware. The principle of the method is to map keystroke events on the remote control to virtual touch based events according to specific mapping relationship corresponding to each application. Since the mapping relationship is various in each scene within one application, scenes should be recognized with feature information before the mapping process. The feature information and the mapping relationship in each scene have been set up prior to running of the application. When one application is running, the current scene of the application could be identified by scene recognition algorithm, the mapping relationship related to the current scene is able to be acquired, and then keystrokes on the remote control would be mapped to touch based events. The proposed method is tested on a smart television platform, and the result indicates the method can operate most applications by remote control, while the input response delay brought by the event mapping is negligibly less than one millisecond.



ABSTRACT

Verilog code for an alarm clock on FPGA is presented in this project. The Verilog code is fully synthesizable for FPGA implementation.

The alarm clock outputs a real-time clock with a 24-hour format and also provides an alarm feature. Users also can set the clock time through switches.



ABSTRACT

In this project, Verilog code for FIFO memory is presented. The First-In-First-Out (FIFO) memory with the following specification is implemented in Verilog:

  • 16 stages
  • 8-bit data width 
  • Status signals: 
  1. Full: high when FIFO is full else low.
  2. Empty: high when FIFO is empty else low.
  3. Overflow: high when FIFO is full and still writing data into FIFO, else low
  4. Underflow: high when FIFO is empty and still reading data from FIFO, else low.
  5. Threshold: high when the number of data in FIFO is less than a specific threshold, else low.



ABSTRACT

A Verilog source code for a traffic light controller on FPGA is presented. A sensor on the farm is to detect if there are any vehicles and change the traffic light to allow the vehicles to cross the highway. Otherwise, highway light is always green since it has higher priority than the farm.



ABSTRACT

This project presents a car parking system in VHDL using Finite State Machine (FSM). There switched to STOP state and the Red LED will be blinking so that the next car will be noticed to stop and enter the password. After the car passes the gate and gets into the car park, the FSM returns to IDLE state.is a front sensor to detect vehicles going to the gate of the car parking system. Another back sensor is to detect if the coming vehicle passed the gate and getting into the car park.

The car parking system in VHDL operates under the control of a Finite State Machine (FSM) as follows:

Initially, the FSM is in IDLE state. If there is a vehicle coming detected by the front sensor, FSM is switched to WAIT_PASSWORD state for 4 cycles. The car will input the password in this state; if the password is correct, the gate is opened to let the car get in the car park and FSM turns to RIGHT_PASS state; a Green LED will be blinking. Otherwise, FSM turns to WRONG_PASS state; a Red LED will be blinking and it requires the car to enter the password again until the password is correct. When the current car gets into the car park detected by the back sensor and there is the next car coming, the FSM is switched to STOP state and the Red LED will be blinking so that the next car will be noticed to stop and enter the password. After the car passes the gate and gets into the car park, the FSM returns to IDLE state.



ABSTRACT

SPI(Serial Peripheral Interface) Master core synchronous serial interface between different devices such as microcontrollers, DACs, ADCs and other.

Features:

  • Full duplex synchronous serial data transfer
  • Variable length of transfer word up to128bits
  • MSB or LSB first data transfer
  • Rx and Tx on both rising or falling edge of serial clock independently
  • 8slave select lines
  • fully static synchronous design with one clock domain
  • Technology independent Verilog
  • Fully synthesizable



ABSTRACT

This describes a 64-bit x 4096-MB (4GB) synchronous/asynchronous, true dual-port RAM design with any combination of independent read or write operations in the same clock cycle in Verilog HDL. The design unit dynamically switches between read and write operations with the write enable input of the respective port. Design is verified with verilog test bench using EDA Synthesis tools.



Address

IEEEProjectz Bangalore:
#14/2, 2nd Floor, Next to Total Gaz, Near GT mall, Magadi main road, Bangalore-23.

IEEEProjectz Mysore:
#1, 2nd Floor, Namratha Complex, Near Saraswathi Theatre, Kamakshi Hospital Road, Saraswathipuram, Mysore-570009.

IEEEProjectz Mangalore:
#32, 1st Floor, Near Westline Signature, Nanthoor, Kadri, Mangalore-575005.

IEEEProjectz Hassan:
#87, 3rd Floor, Above SBI ATM, Near Mission Hospital, RC Road, Hassan-573201.